The subject matter disclosed herein relates to lookaside buffers and more particularly relates to bypassing traversing a lookaside buffer when an identifier targeted by an invalidate command is found in a filter.
A processor of a computing device often includes multiple cores and some computing devices are configured for a user to divide computing resources to create a virtual machine situated on a logical partition. A logical partition is often capable of running a separate instance of an operating system. The processor may include multiple memory management units (“MMUs”) where one MMU may be external to the cores and may manage common memory. Virtual machines typically use virtual or effective addresses that are different than physical addresses.
A lookaside buffer, such as a translation lookaside buffer (“TLB”) stores effective addresses paired with physical addresses and has a limited number of memory locations and is typically much smaller than an effective address range and/or a physical address range. Often a hash function is used to map an address from a large address space to a smaller address space of a lookaside buffer. Often the lookaside buffer includes multiple entry locations for a particular hash to handle multiple effective or physical addresses having an identical hash. Each effective address in the lookaside buffer is paired with a physical address. In addition, each address pair is linked to a particular process identifier (“PID”) of a logical partition identifier (“LPID”) so that an address pair is mapped to a PID of a LPID in the lookaside buffer.
When an invalidate command is issued for a particular address, the hash function may be used to locate and invalidate a particular effective address/physical address pair. However, when a PID invalidate command is issued to invalidate all addresses of a particular process (identified by PID) of a partition (identified by LPID), currently execution of the PID invalidate command requires accessing each location of the lookaside buffer in search of the addresses that are linked to the PID targeted by the PID invalidate command, which is a time-intensive process. Often, the processor slows processing of commands as a search based on the PID invalidate command walks through each memory location looking for addresses linked to a PID targeted by the PID invalidate command. An LPID invalidate command, which invalidates all addresses for a particular LPID has even greater performance demands than a PID invalidate command.